Variable resistance nonvolatile memory device and method of writing thereby

摘要

Provided is a variable resistance nonvolatile memory device that achieves, in multi-bit simultaneous writing for increasing a writing speed, writing with little variation caused by positions of memory cells in multi-bit simultaneous writing. The variable resistance nonvolatile memory device includes bit lines, word lines, memory cells, a first write circuit (e.g., a write circuit (60-0)), a second write circuit (e.g., a write circuit (60-k−1)), a first selection circuit (e.g., a selection circuit (S0—0)), a second selection circuit (e.g., a selection circuit (S0_k−1)), and a first word line drive circuit (a word line drive circuit (40-1)), wherein the first selection circuit (e.g., an NMOS transistor (TS0—0—0 to TS0—0_m−1) included in the selection circuit) has a greater ON resistance than the second selection circuit (e.g., an NMOS transistor (TS0_k−1—0 to TS0_k−1_m−1) included in the selection circuit) does.

主权项

1. A variable resistance nonvolatile memory device comprising:
a plurality of bit lines; a plurality of word lines that cross the bit lines; a plurality of memory cells at cross points of the bit lines and the word lines, the memory cells each including at least a variable resistance element and reversibly changing at least between a first resistance state and a second resistance state; a first write circuit that applies a write voltage to a first bit line that is at least one of the bit lines, where, among the memory cells, memory cells connected to the first bit line are grouped together as a first memory cell array; a second write circuit that applies a write voltage to a second bit line that is at least one of the bit lines and is different from the first bit line, where, among the memory cells, memory cells connected to the second bit line are grouped together as a second memory cell array; a first selection circuit that connects or disconnects at least one of the first write circuit and the first bit line; a second selection circuit that connects or disconnects at least one of the second write circuit and the second bit line; and a first word line drive circuit that selectively drives the word lines, wherein the memory cells include a memory cell for data storage and a memory cell not for data storage, the first write circuit and the second write circuit simultaneously apply the write voltage to the first bit line and the second bit line, respectively, memory cells to which the first write circuit and the second write circuit simultaneously write include the memory cell for data storage and the memory cell not for data storage that are on a same word line, the first memory cell array is placed closer to the first word line drive circuit than the second memory cell array is, and a first ON resistance is greater than a second ON resistance, the first ON resistance being a resistance value of the first selection circuit when the first selection circuit connects the first write circuit and the first bit line, and the second ON resistance being a resistance value of the second selection circuit when the second selection circuit connects the second write circuit and the second bit line.