Semiconductor integrated circuit and nonvolatile semiconductor storage device

摘要

A semiconductor integrated circuit according to an embodiment includes an oscillator that generates and outputs an oscillation signal in an active state and generates no oscillation signal in an inactive state. The semiconductor integrated circuit includes a negative charge pump that generates an output voltage that is a negative voltage in response to the oscillation signal and outputs the output voltage to an output pad. The semiconductor integrated circuit includes a negative voltage detecting circuit that detects the output voltage and controls the oscillator to be in the active state or inactive state so as to bring the output voltage close to a target voltage.

主权项

1. A semiconductor integrated circuit, comprising:
an oscillator that generates and outputs an oscillation signal in an active state and generates no oscillation signal in an inactive state; a negative charge pump that generates an output voltage that is a negative voltage in response to the oscillation signal and outputs the output voltage to an output pad; and a negative voltage detecting circuit that detects the output voltage and controls the oscillator to be in the active state or inactive state so as to bring the output voltage close to a target voltage, the negative voltage detecting circuit comprises: a first pMOS transistor connected to a power supply at a source thereof; a first resistor connected to a drain of the first pMOS transistor at a first end thereof and to a ground at a second end thereof; a first comparator that controls a gate voltage of the first pMOS transistor in such a manner that a first voltage between the first end of the first resistor and the drain of the first pMOS transistor is equal to a reference voltage; a second pMOS transistor that is connected to the power supply at a source thereof and through which a second current, which is a mirror current of a first current flowing through the first pMOS transistor, flows; a second resistor connected to a drain of the second pMOS transistor at a first end thereof; a third resistor connected to a second end of the second resistor at a first end thereof and to the output pad at a second end thereof; a first test switch element connected to the second end of the second resistor at a first end thereof and to the ground at a second end thereof; and a second comparator that compares a second voltage between the first end of the second resistor and the drain of the second pMOS transistor with the reference voltage, outputs an activation signal that activates the oscillator if the second voltage is lower than the reference voltage, and outputs a deactivation signal that deactivates the oscillator if the second voltage is equal to or higher than the reference voltage, and in a test, the negative voltage detecting circuit turns on the first test switch element to perform such a control as to insulate an output of the negative charge pump and the second end of the third resistor from each other or deactivate the negative charge pump, and then changes a value of the second current so as to switch the output of the second comparator from the activation signal to the deactivation signal or from the deactivation signal to the activation signal, and in a normal operation in which the negative charge pump operates in response to the output of the second comparator, the negative voltage detecting circuit turns off the first test switch element and fixes the value of the second current at a value at the time when the switching of the output of the second comparator occurs in the test.