Isolated modulator circuit with synchronized pulse generator for self-monitoring reset with capacitively-coupled isolation barrier

摘要

Self-monitoring reset circuitry is presented for use in analog-to-digital converters and other modulator circuitry with capacitively coupled isolation barriers in which the modulator output data is monitored for inactivity by a reset circuit synchronized to the modulator clock, and extra pulses are selectively introduced into the data prior to transmission across the isolation barrier if no modulator state changes occur within a predetermined number of clock cycles to provide a predictable data output value for each end of the analog input range and to reset the output to the correct state in situations where transient noise toggles the output and the modulator output is static.

主权项

1. An isolated modulator circuit, comprising:
a modulator providing a modulator output signal based at least partially on an analog input and a modulator clock signal; a pulse generation circuit receiving the modulator output signal and being configured to provide a data output signal comprising pulses from the modulator output signal based at least partially on the modulator output signal and the modulator clock signal, the pulse generation circuit being configured to provide at least one additional pulse edge in the data output signal responsive to lack of state changes in the modulator output signal for a predetermined number of clock cycles of the modulator clock signal, the at least one additional pulse edge being synchronized to the modulator clock signal; a transmitter circuit receiving the data output signal and being configured to provide a differential transmit output signal at first and second transmit output lines; an isolation circuit comprising:
a first capacitor with a first terminal connected to the first transmit output line and a second terminal connected to a first receiver input line, anda second capacitor with a first terminal connected to the second transmit output line and a second terminal connected to a second receiver input line; a receiver circuit receiving a receiver differential input signal at the first and second receiver input lines and configured to provide a pulse output signal representing the data output signal based at least partially on the receiver differential input signal.