发明名称 Switched capacitor circuit utilizing delayed control signal and inverting control signal for performing switching operation and related control method
摘要 A switched capacitor circuit includes an inverter, a first capacitor, and a first switch unit. The inverter is arranged to receive a control signal to generate an inverting control signal corresponding to the control signal. The first capacitor is coupled between a first output port and a first node. The first switch unit is arranged to receive a first input signal and a second input signal, and selectively couple the second input signal to the first node according to the first input signal. The first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal.
申请公布号 US8860492(B2) 申请公布日期 2014.10.14
申请号 US201313861363 申请日期 2013.04.11
申请人 Realtek Semiconductor Corp. 发明人 Yang Yu-Che
分类号 H03K17/28;H03H19/00 主分类号 H03K17/28
代理机构 代理人 Hsu Winston;Margo Scott
主权项 1. A switched capacitor circuit, comprising: an inverter, for receiving a control signal to generate an inverting control signal corresponding to the control signal; a first capacitor, coupled between a first output port and a first node; a delay unit, for delaying a first input signal to generate the delayed first input signal; and a first switch unit, coupled to the delay unit, the first switch unit arranged for receiving the delayed first input signal and a second input signal, and selectively coupling the second input signal to the first node according to the delayed first input signal; wherein the first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal; and after a signal level of the control signal is switched, the first switch unit receives the delayed first input signal corresponding to the control signal with the switched signal level at a time later than a time at which the first switch unit receives the second input signal corresponding to the control signal with the switched signal level.
地址 Science Park, HsinChu TW