LOW-POWER CML-LESS TRANSMITTER ARCHITECTURE

摘要

An exemplary embodiment of the present invention relates to a high-speed and low-power transmitter not using a current mode logic circuit. The transmitter comprises a main multiplexer formed to generate a main data signal by multiplexing a parallel signal; a secondary multiplexer formed to generate a post data signal by multiplexing the parallel signal; and multiple output drivers formed to generate a pre-emphasized signal by adding the main data signal and the post data signal.