| 发明名称 |
CIRCUITS AND METHODS FOR DQS AUTOGATING |
| 摘要 |
In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer. |
| 申请公布号 |
US2014269117(A1) |
申请公布日期 |
2014.09.18 |
| 申请号 |
US201313829881 |
申请日期 |
2013.03.14 |
| 申请人 |
Altera Corporation |
发明人 |
Maryan Krzysztof;Chiu Gordon Raymond;Nordyke Warren;Azizi Navid |
| 分类号 |
G11C8/18 |
主分类号 |
G11C8/18 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
receiving, by a configurable circuit, a differential strobe signal comprised of a first component and a second component; buffering, by a first buffer, both the first component and the second component of the differential strobe signal; buffering, by a second buffer, the first component of the differential strobe signal; receiving, by a control logic block, the output of the second buffer; after a period when the values of both the first component and the second component of the differential strobe signal are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting, by the control logic block, a transition in the first component of the differential strobe signal from the first logic state to a second logic state; in response to the detection of the transition, asserting, by the control logic block, an enable signal; receiving, by a gating logic block, the enable signal and the output of the first buffer; and when the enable signal is asserted, un-gating, by the gating logic block, the output of the first buffer such that the output of the first buffer is passed through the gating logic block. |
| 地址 |
US |
