发明名称 |
Arithmetic processing unit and control method for cache hit check instruction execution |
摘要 |
According to an aspect of an embodiment of the invention, an arithmetic processing unit includes a first cache memory unit that holds a part of data stored in a storage device; an address register that holds an address; a flag register that stores flag information; and a decoder that decodes a prefetch instruction for acquiring data stored at the address in the storage device. The arithmetic processing unit further includes an instruction execution unit that executes a cache hit check instruction instead of the prefetch instruction on the basis of a decoded result when the flag information is held, the cache hit check instruction allowing for searching the first cache memory unit with the address to thereby make a first cache hit determination that the first cache memory unit holds the data stored at the address in the storage device. |
申请公布号 |
US8707014(B2) |
申请公布日期 |
2014.04.22 |
申请号 |
US20100929021 |
申请日期 |
2010.12.22 |
申请人 |
YAMAZAKI IWAO;IMAI HIROYUKI;FUJITSU LIMITED |
发明人 |
YAMAZAKI IWAO;IMAI HIROYUKI |
分类号 |
G06F9/00 |
主分类号 |
G06F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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