发明名称 |
Latency tolerant system for executing video processing operations |
摘要 |
A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations, and a vector execution unit coupled to the host interface and configured to execute vector video processing operations. A command FIFO is included for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A DMA engine is built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading the command FIFO with data and instructions for the vector execution unit. |
申请公布号 |
US8687008(B2) |
申请公布日期 |
2014.04.01 |
申请号 |
US20050267875 |
申请日期 |
2005.11.04 |
申请人 |
KARANDIKAR ASHISH;GADRE SHIRISH;LEW STEPHEN D.;NVIDIA CORPORATION |
发明人 |
KARANDIKAR ASHISH;GADRE SHIRISH;LEW STEPHEN D. |
分类号 |
G06F15/16;G06F7/32;G06F13/00;G06F13/14;G06F15/00;G06F15/80;G09G5/36;G09G5/39 |
主分类号 |
G06F15/16 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|