发明名称 Reducing power consumption in a segmented memory
摘要 A memory structure can include a first memory block including a plurality of memory cells corresponding to a first subset of addresses of a range of addresses and a second memory block including a plurality of memory cells corresponding to a second subset of addresses of the range of addresses. The memory structure can include control circuitry coupled to the first memory block and the second memory block and configured to provide control signals to the first memory block and the second memory block. The first memory block and the second memory block can be configured to implement a reduced power mode independently of one another responsive to the control signals.
申请公布号 US8503264(B1) 申请公布日期 2013.08.06
申请号 US201113300512 申请日期 2011.11.18
申请人 NARAYANAN SRIDHAR;SUBRAMANIAN SRIDHAR;KLEIN MATTHEW H.;CROTTY PATRICK J.;XILINX, INC. 发明人 NARAYANAN SRIDHAR;SUBRAMANIAN SRIDHAR;KLEIN MATTHEW H.;CROTTY PATRICK J.
分类号 G11C5/14 主分类号 G11C5/14
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