发明名称 |
Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers |
摘要 |
A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed. |
申请公布号 |
US2013009307(A1) |
申请公布日期 |
2013.01.10 |
申请号 |
US201113179299 |
申请日期 |
2011.07.08 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.;LU WEN-HSIUNG;CHENG MING-DA;LIN CHIH-WEI;WU YI-WEN;LIN HSIU-JEN;LIU CHUNG-SHI;LII MIRNG-JI;YU CHEN-HUA |
发明人 |
LU WEN-HSIUNG;CHENG MING-DA;LIN CHIH-WEI;WU YI-WEN;LIN HSIU-JEN;LIU CHUNG-SHI;LII MIRNG-JI;YU CHEN-HUA |
分类号 |
H01L23/498;H01L21/60 |
主分类号 |
H01L23/498 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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