发明名称 |
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF |
摘要 |
<p>PURPOSE: An integrated circuit packaging system with vertical interconnections and a manufacturing method for same are provided to mount a second substrate on a non-active layer of an integrated circuit, thereby reducing the size of a package. CONSTITUTION: Vertical interconnections(110) are adhered along the peripheral part of a first substrate(104). An integrated circuit(114) is mounted on the first substrate. The vertical interconnections surround the integrated circuit. A second substrate(124) is mounted on the vertical interconnections and the integrated circuit.</p> |
申请公布号 |
KR20130000319(A) |
申请公布日期 |
2013.01.02 |
申请号 |
KR20120051050 |
申请日期 |
2012.05.14 |
申请人 |
STATS CHIPPAC LTD. |
发明人 |
HAN, BYUNG JOON;YOON, IN SANG;BAE, JO HYUN |
分类号 |
H01L23/525 |
主分类号 |
H01L23/525 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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