发明名称 |
Triple loop clock and data recovery (CDR) |
摘要 |
In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream. |
申请公布号 |
US8300753(B2) |
申请公布日期 |
2012.10.30 |
申请号 |
US20090510160 |
申请日期 |
2009.07.27 |
申请人 |
NEDOVIC NIKOLA;TZARTZANIS NESTOR;WALKER WILLIAM W.;FUJITSU LIMITED |
发明人 |
NEDOVIC NIKOLA;TZARTZANIS NESTOR;WALKER WILLIAM W. |
分类号 |
H04L7/00 |
主分类号 |
H04L7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|