发明名称 Method and system for verification of multi-voltage circuit design
摘要 Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
申请公布号 US8255859(B2) 申请公布日期 2012.08.28
申请号 US20090467955 申请日期 2009.05.18
申请人 CHILWAL HARSH;JADCHERLA SRIKANTH;KOTNI SRIRAM;TIWARI PRAPANNA;SYNOPSYS, INC. 发明人 CHILWAL HARSH;JADCHERLA SRIKANTH;KOTNI SRIRAM;TIWARI PRAPANNA
分类号 G06F17/50;G06F9/455 主分类号 G06F17/50
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