发明名称 TWO REGISTER PARALLEL BINARY ADDER/SUBTRACTOR
摘要 Binary arithmetic member for adding and subtracting binary numbers, in which the input register and the accumulator have connected between them a control-device comprising a sensing circuit for sensing the least significant bit place, where the binary number to be added or subtracted has a bit value "1," whose outputs corresponding to the respective bit places of the binary number are connected to the corresponding inputs of the accumulator so that under the control of a starting pulse that bistable flip-flop of the accumulator changes its state which ordinally corresponds to said least significant bit place where the binary number to be added or subtracted has a bit value "1," said control-device comprising furthermore a gate circuit which, together with the sensing circuit, satisfies a given logical equation, so that a simple arithmetic member is obtained. A special device is provided for adding to or subtracting from the result in the accumulator an additional binary number 1 when the accumulator passes the zero position (FIGS. 2, 2a, 2b, 2c, 2d).
申请公布号 US3676657(A) 申请公布日期 1972.07.11
申请号 USD3676657 申请日期 1970.06.04
申请人 U.S. PHILIPS CORP. 发明人 EELTJE DE BOER
分类号 G06F7/50;G06F7/509;(IPC1-7):G06F7/50 主分类号 G06F7/50
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