发明名称 |
Serial bus clock frequency calibration system and method thereof |
摘要 |
A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost. |
申请公布号 |
US8140882(B2) |
申请公布日期 |
2012.03.20 |
申请号 |
US20090388373 |
申请日期 |
2009.02.18 |
申请人 |
LEE WEI-TE;YANG SHIN-TE;CHU YEN-FAH;GENESYS LOGIC, INC. |
发明人 |
LEE WEI-TE;YANG SHIN-TE;CHU YEN-FAH |
分类号 |
H03D3/24 |
主分类号 |
H03D3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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