| 摘要 |
A pattern detection circuit detects a pattern in a received bit stream, for example a repetitive 8-bit silence pattern in a stream of digital audio data. Summing circuitry forms during first alternate time periods a sum of a first sequence comprising a predetermined number of alternate bits in the bit stream; and forms during second alternate time periods an inverse of a sum of a second sequence comprising the predetermined number of alternate bits in the bit stream. It is then determined whether successive sums formed by the summing circuitry are equal. |
