| 摘要 |
A semiconductor memory device including a bit test circuit with an ignore function is provided. The semiconductor memory device includes a memory cell array and a bit test circuit. The memory cell array includes a plurality of memory cells. The bit test circuit is configured to perform a parallel bit test to determine defective memory cells based on bits received from the plurality of memory cells, a tester signal for each of the plurality of memory cells, and a mode register set signal for each of the plurality of memory cells. The bit test circuit is also configured to output a non-defective pass signal for at least one of the plurality of memory cells based on at least one of the at least one bit received from the at least one memory cell, the tester signal for the at least one memory cell and the mode register set signal for the at least one memory cell. |
