发明名称
摘要 <p>A multi processor system having a first processor; and one or more second processors is provided. Each of the one or more second processors is connected to the first processor by a dedicated interrupt signal line. Upon receiving a first interrupt signal indicating a power cutoff event, the first processor sends via the dedicated interrupt signal line a second interrupt signal to at least one second processor among the one or more second processors.</p>
申请公布号 JP4687399(B2) 申请公布日期 2011.05.25
申请号 JP20050322595 申请日期 2005.11.07
申请人 发明人
分类号 G06F1/32;G06F1/26;G06F1/30 主分类号 G06F1/32
代理机构 代理人
主权项
地址