发明名称 PREPREG AND MULTILAYER PRINTED WIRING BOARD
摘要 PROBLEM TO BE SOLVED: To provide a prepreg for buildup that can suppress exposure of a base material by suppressing dissolution of an insulating resin layer exposed on an inner peripheral surface of a via hole during desmear processing, and also secure continuity reliability by suppressing remaining of a resin between a conductor circuit of an inner-layer circuit board on a bottom surface of the via hole and plating in the via hole, and a multilayer printed wiring board using the same. SOLUTION: The prepreg for buildup includes a low-solubility resin layer containing the base material in a low-solubility resin in a B stage which is low in solubility in chemicals during the desmear processing and a high-solubility resin layer provided on one surface of the low-solubility resin layer and composed of a high-solubility resin in the B stage relatively higher in solubility in the chemicals during the desmear processing than the low-solubility resin. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011096741(A) 申请公布日期 2011.05.12
申请号 JP20090247118 申请日期 2009.10.27
申请人 PANASONIC ELECTRIC WORKS CO LTD 发明人 ARAKI SHUNJI;TAMIYA HIROKI;NAKAMURA YOSHIHIKO
分类号 H05K3/46;H05K3/42 主分类号 H05K3/46
代理机构 代理人
主权项
地址