| 摘要 |
A display apparatus includes a delay generation circuit that generates a reference signal and a competing signal, the competing signal being generated based on a delay set signal, an input order judgment circuit that judges an input order of the reference signal and the competing signal, a delay set circuit that generates the delay set signal based on a judgment result in the input order judgment circuit, and an internal synchronous control circuit that controls transfer of display data between a CPU and a display panel. An operation test of the internal synchronous control circuit is performed using the reference signal and the competing signal. Hence, fault coverage can be enhanced.
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