发明名称 CIRCUIT LAYOUT STRUCTURE AND METHOD TO SCALE DOWN IC LAYOUT
摘要 A circuit layout structure includes a substrate including a first region and a second region, and a set of conductive lines including a first conductive line and a second conductive line which respectively pass through the first region and the second region, wherein a variable spacing lies between the first conductive line and the second conductive line and the first conductive line and the second conductive line selectively have a first region line width and a second region line width so that the first region line width and the second region line width are substantially different.
申请公布号 US2010320558(A1) 申请公布日期 2010.12.23
申请号 US20090487631 申请日期 2009.06.18
申请人 CHANG HSIEN-CHANG 发明人 CHANG HSIEN-CHANG
分类号 H01L27/02;G06F17/50 主分类号 H01L27/02
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