发明名称 |
Apparatus for low-jitter frequency and phase locked loop and associated methods |
摘要 |
A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.
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申请公布号 |
US7825737(B1) |
申请公布日期 |
2010.11.02 |
申请号 |
US20080334701 |
申请日期 |
2008.12.15 |
申请人 |
MARVELL INTERNATIONAL LTD. |
发明人 |
FANG STEVE;CHENG CHI FUNG |
分类号 |
H03L7/087 |
主分类号 |
H03L7/087 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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