发明名称 On-chip multiprocessor system
摘要 The system has a generalist processor (GPP) for implementing a set of instructions, which define a set of operations to be executed by the processor. Calculation tiles (310-1, 310-4, 310-6, 310-11, 310-14) are connected between them by a communication network (320) that is accessed by an accessing unit. The calculation tiles include an accelerator coupled to the processor, where the accelerator accelerates calculation tasks of the processor. Each calculation tile is provided with a local memory.
申请公布号 EP2192482(A1) 申请公布日期 2010.06.02
申请号 EP20090176582 申请日期 2009.11.20
申请人 THALES 发明人 YEHIA, SAMI
分类号 G06F9/38;G06F15/78;G06F15/80 主分类号 G06F9/38
代理机构 代理人
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