| 摘要 |
An adder is provided for adding input signals including first and second binary input numbers, with N bits each. The adder includes a determination circuit capable of determining the bits of the sum of the input signals. The determination circuit includes an estimating circuit including estimating blocks connected in series, each estimating block being capable of estimating each bit of the sum, and a correction circuit capable of generating a correction signal so as to correct each estimated bit of the sum after each estimate. Each correction signal of an estimated bit rank i of the sum is generated using the last rank i-1 estimated and corrected bit of the sum, the correction signal of said last rank i-1 bit, and the last estimated and corrected rank i-2 bit of the sum.
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