| 摘要 |
A bit line equalizing control circuit of a semiconductor memory apparatus is provided to improve RAS precharge time by increasing the timing of releasing equalizing of a bit line and a bit bar line. A control signal generating unit(100) receives a bank active signal and generates a control signal, and a bit line equalizing selecting unit(200) produces a bit line equalizing sensing signal in response to a plurality of mat selection signals and a control signal. The bit line equalizing selecting unit comprises a signal combination unit and a sensing signal generator, and the signal combination unit combines a plurality of mat select signals. A sensing signal generator receives an output of the signal combination unit and a control signal and generates a signal of sensing a bit line equalizing.
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