CLOCK SIGNAL DISTRIBUTION NETWORK AND METHOD FOR CLOCK SIGNAL DISTRIBUTION OF SEMICONDUCTOR CHIP

摘要

A clock signal distribution network and a method for distributing a clock signal of a semiconductor chip are provided to improve jitter and skew characteristics of a clock signal. A clock signal source(310) of a clock signal distribution network(300) generates an internal clock signal in which jitter and noise are reduced by receiving an external clock signal. A signal distributor(320) distributes the internal clock signal. The signal distributor is laminated in a lower part of the clock signal source. An integrated circuit(330) comprises a circuit device which operates by using the clock signal distributed through the signal distributor. The integrated circuit is laminated in a lower pat of the signal distributor.