| 摘要 |
In an electronic device having a plurality of processing elements PEs that operate in synch with a clock signal, each of the plurality of PEs generates its own operating clock signal in accordance with a clock enable signal that is input together with data from an outside or from a PE of a preceding stage, processes the input data in response to this operating clock signal, outputs this processed data to a PE of a succeeding stage and outputs the clock enable signal to the PE of the succeeding stage, and halts generation of its own operating clock signal when output of the processed data is completed following completion of processing of the data. |
