发明名称 Method for manufacturing integrated circuit
摘要 The flatness of the surface of the light-receiving portion must be increased when the upper structural layer of a light detector is etched. The present invention provides a method for manufacturing an integrated circuit in which an aperture is formed in a stack in which an underlayer, a light-receiving area pad, and an upper structural layer are layered on a substrate, the method comprising a light-receiving area pad etching step for etching the structural layer and the light-receiving area pad under etching conditions in which a high selectivity ratio is maintained between the upper structural layer and the light-receiving area pad; and an underlayer etching step for switching to etching conditions in which the light-receiving area pad has a high selectivity ratio in relation to the underlayer following the light-receiving area pad etching step, and etching the light-receiving area pad and the underlayer. The bottom surface of the aperture can thereby be made flatter and the amount of incident light in the plane of the light-receiving portion can be made more uniform.
申请公布号 US7462567(B2) 申请公布日期 2008.12.09
申请号 US20070790230 申请日期 2007.04.24
申请人 SANYO ELECTRIC CO., LTD. 发明人 YAMADA TETSUYA;IMAI TSUTOMU
分类号 H01L21/302;H01L21/461 主分类号 H01L21/302
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