| 摘要 |
An asymmetric flip-flop for reducing a leakage current is provided to reduce a leakage current by selectively increasing a gate length of transistor as a leakage source based on an input signal, an output signal and a pulse signal. An asymmetric flip-flop for reducing a leakage current includes a master terminal(210), and a slave terminal(260). The master terminal latches input data when a clock signal is a first level. The slave terminal receives and outputs the input data latched to the master terminal when the clock signal is a second level. The master terminal includes a first group of inverters(220,230,240,250). The inverters selectively have transistors with a gate-length bias in response to the input data value. The slave terminal has a second group of inverters(270,280,290). The inverters selectively have transistors with a gate-length bias in response to the output value. |
