| 摘要 |
<p>A signal receiving device is provided with N-set signal receiving blocks (N is an integer equal to not less than 2), and receives N serial signals and N clock signals with an equal cycle. A first signal receiving block is provided with a phase difference detecting circuit for generating a phase difference signal indicative of a phase difference between a first clock signal and a first internal clock signal, a first phase delay circuit for delaying a phase of the first clock signal in accordance with the phase difference signal, and a serial-to-parallel conversion circuit for converting a first set serial signal based on the first internal clock signal. Other n-th signal receiving block is provided with an n-th phase delay circuit for delaying a phase of an n-th clock signal in accordance with a phase difference value of a phase different signal from the first signal receiving block to generate an n-th internal clock signal, and a serial-to-parallel conversion circuit for converting n-set serial signals based on the n-th internal clock signal.</p> |
