发明名称 CLOCK GENERATION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock generation circuit capable of detecting a frequency variation due to the aging of an oscillator working as a clock source without measuring a frequency at periodical maintenance. <P>SOLUTION: This circuit comprises an acting clock generation circuit 100 for generating a clock signal corresponding to an OCVCXO102 output to be controlled by the control voltage and a standby clock generation circuit 200 for generating a clock signal according to the OCVCXO output to be controlled by the control voltage determined in a way that synchronization with the acting clock generation circuit 100 takes place through a reference signal "REFn" generated by the OCVCXO102 output. This circuit monitors a control voltage value to detect a frequency variation in the OCVCXO102. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007251925(A) 申请公布日期 2007.09.27
申请号 JP20070006910 申请日期 2007.01.16
申请人 NEC SAITAMA LTD 发明人 KUWAJIMA NAOKI
分类号 H03L7/00;H03L7/095 主分类号 H03L7/00
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