Method for high-level synthesis of semiconductor integrated circuit

摘要

A Control Data Flow Graph (CDFG) which is an intermediate representation obtained by analyzing a behavioral-level circuit description of hardware, is subjected to a process of changing a shape of the CDFG by adding an operation before or after scheduling, so as to conceal design information. A CDFG to which a hardware resource has been allocated may be subjected to a process of changing the allocation of the hardware resource.