发明名称 Buffer circuit and integrated circuit
摘要 In a two-stage inverter circuit including an inverter circuit constituted by first and second FETs and an inverter circuit constituted by two FETs, a source and a gate of a third FET are connected to a first power source and a second power source, respectively. A drain of the third FET is connected to a source of the first FET. A source and a gate of a fourth FET are connected to the first power source and the second power source, respectively. A drain of the fourth FET is connected to a source of a seventh FET. A gate of the seventh FET is connected to the second power source, and a drain of the seventh FET is connected to a back gates of the first, third, fourth, seventh and fifth FETs. The drain of the third FET is connected to the drain of the fourth FET.
申请公布号 US2006164134(A1) 申请公布日期 2006.07.27
申请号 US20050117383 申请日期 2005.04.29
申请人 FUJITSU LIMITED 发明人 UNO OSAMU
分类号 H03B1/00 主分类号 H03B1/00
代理机构 代理人
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