发明名称 |
Large-input-delay variation tolerant (LIDVT) receiver adopting FIFO mechanism |
摘要 |
The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an input data and outputs the input data. An output stage selector sequentially generates a control signal. And a multiplexer selectively outputs the input data from the N-stage FIFO.
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申请公布号 |
US7039144(B2) |
申请公布日期 |
2006.05.02 |
申请号 |
US20010860518 |
申请日期 |
2001.05.21 |
申请人 |
SILICON INTEGRATED SYSTEMS CORPORATION |
发明人 |
CHEN YI-HUNG;LEE MING-SHIEN;KUO JEW-YONG |
分类号 |
H04L25/00;H03M9/00;H04L7/00;H04L7/02;H04L25/05 |
主分类号 |
H04L25/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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