发明名称 LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To accomplish automatic layout of an area pad and a wiring pattern around the same. SOLUTION: At least one cell out of multiple cells is prepared as area pad cells 1 to 3; at least one in other cells is prepared as wiring pattern cells 4 to 10, and stored in a design library; and, based on this design library and cell arrangement information or wiring structure information prepared in advance, arrangement positions of the area pad cell and the wiring pattern cell are calculated to allow automatic arrangement. Thus, while securing connections between cells or cells and other patterns by the pins and contacts of the wiring on the cell boundary and in the cell, a layout design can be generated that satisfies the design rule. At the same time, a usual automatic layout is performed to generate a layout database having comprehensive layout information. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006049782(A) 申请公布日期 2006.02.16
申请号 JP20040232530 申请日期 2004.08.09
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KONISHI MASAFUMI
分类号 H01L21/82;G06F17/50;H01L21/822;H01L27/04 主分类号 H01L21/82
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