| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory controller capable of improving the efficiency of data transfer execution for a memory (e.g., SDRAM). SOLUTION: This memory controller 100 is provided with a BANK/ROW address comparison section 7, and a refresh request generation section 8. The BANK/ROW address comparison section 7 is a circuit for comparing a first address in active ROW information with a second address in a memory access request for an SDRAM 300. The refresh request generation section 8 is a circuit for generating a refresh request for the SDRAM 300 according to the comparison results of the BANK/ROW address comparison section 7. COPYRIGHT: (C)2006,JPO&NCIPI
|
