发明名称 |
Method and apparatus for reducing clock speed and power consumption |
摘要 |
A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer. <IMAGE> |
申请公布号 |
EP1207640(A3) |
申请公布日期 |
2005.10.19 |
申请号 |
EP20010308917 |
申请日期 |
2001.10.19 |
申请人 |
ALTIMA COMMUNICATIONS, INC. |
发明人 |
CHANG, MICHAEL;SOKOL, MICHAEL |
分类号 |
G06F1/32;G06F5/06;H04J3/06;H04L12/56 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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