| 摘要 |
A signal processor for a mobile communication system including a plurality of function blocks for signal processing directed to facilitating debugging. A signal processor 100 includes primary function blocks such as an error correction coder block 102 , a modulator block 104 , a demodulator block 202 , an error correction decoder block 204 , and an MPU 302 . More particularly, the signal processor 100 outputs debug information in an arbitrary data length along with time information serially from an arbitrary function block, based on an instruction from an outside, through signal lines 404 ( 1 )~ 404 (I), 404 ( 1 )~ 404 (J), 404 ( 1 )~ 404 (K), 404 ( 1 )~ 404 (L) connected to each function block, a selection multiplex output block 403 , and a selection multiplex output signal line 402 . Hence, a debugger 401 specifies a function block where a failure occurs and specifies the timing of a failure occurrence.
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