发明名称 PWM OUTPUT CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain a PWM output circuit for converting a PWM signal into an analog voltage in which the output potential is fixed to a desired level at the time of standby and current consumption is suppressed. SOLUTION: The PWM output circuit comprises a means for fixing the input of the PWM output circuit to a reference potential or releasing the input at the time of standby, and a means for connecting the output to the reference potential through a resistor. The output is fixed to a desired potential by selecting the resistance of the resistor connected to the reference potential appropriately. Since power of the circuit is reduced except the resistor connected with the reference potential and the output, current consumption is reduced. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005184313(A) 申请公布日期 2005.07.07
申请号 JP20030420663 申请日期 2003.12.18
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ARAKAWA TETSUO;MIYATA YOSHINORI
分类号 H03M1/66;H03F1/02;H03F3/217;(IPC1-7):H03F1/02 主分类号 H03M1/66
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