| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a signal processor allowing a CPU to access its external memory in an interval of data access in a data length variable DSP. <P>SOLUTION: In the case of 24-bit mode, an instruction from a control part 12 giving an instruction for weighting access from a CPU 111 to an external memory 102 when a determination part 11 determines that access from the DSP1 to the external memory 102 is made. In the case of 16-bit mode, an instruction is given from the control part 12 to an address/data switch part 13 by using an unused third bus cycle, and access from the CPU 111 to the external memory 102 is allowed. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
