发明名称 |
Burn in system and method for improved memory reliability |
摘要 |
A system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The system and method includes writing a logic 0 into all the memory cells in a memory structure. All the high address predecoded lines and alternating predecoded lines for the lowest address are enabled. A voltage drop between neighboring wordlines and bitlines is affected. A logic 1 is written into all the memory cells in the memory structure. An opposite voltage polarity is caused on the bitlines due to the logic 1 in the memory cells. A reverse voltage polarity stress is achieved on the wordlines by flipping the state of the lowest predecoded line (i.e., by changing the input address corresponding to that line.
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申请公布号 |
US6909648(B2) |
申请公布日期 |
2005.06.21 |
申请号 |
US20020101241 |
申请日期 |
2002.03.19 |
申请人 |
BROADCOM CORPORATION |
发明人 |
TERZIOGLU ESIN;WINOGRAD GIL I. |
分类号 |
G11C29/50;(IPC1-7):G11C7/00 |
主分类号 |
G11C29/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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