| 摘要 |
PROBLEM TO BE SOLVED: To provide a SONOS device configured to increase program and erasure efficiency and uniforming the lengths of charge trapping layers over different cells, and to provide a method of manufacturing the same. SOLUTION: The SONOS device is provided with a semiconductor substrate having a first surface, a second surface of a smaller height than the first surface, and a third surface that forms a trench sidewall between the first and second surfaces; a tunnel dielectric layer formed on the semiconductor substrate; a charge trapping layer formed in a form of a spacer on the tunnel dielectric layer on the third surface; a charge isolation layer formed on the tunnel dielectric layer, while covering the charge trapping layer; a gate that is formed to extend from the first surface to the second surface through the third surface covering the charge isolation layer; a first impurity region introduced in the region lying under the first surface, adjacent to the gate; a second impurity region introduced in the region, lying under the second surface and facing the first impurity region. COPYRIGHT: (C)2005,JPO&NCIPI
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