CLOCK ALIGN TECHNIQUE FOR EXCESSIVE STATIC PHASE OFFSET

摘要

A CPU clock signal (314) generated from a phase lock loop (PLL) circuit (312) and a feedback signal (320) of the PLL circuit (312) are used in generating a JBUS clock signal (318). The CPU clock signal (314) and the feedback signal (320) include the same amount of static phase offset introduced by the PLL circuit (312). The CPU clock signal (314) and the feedback signal (320) are input to an alignment detection circuit (316) and used in generating the JBUS clock signal (318). In one embodiment, the JBUS clock signal (318) is generated in synchronization with the CPU clock signal (314) and having the frequency of the feedback signal (320). The present invention reduces or eliminates misalignment of the leading edge of the JBUS clock signal (318) with reference to a specific leading edge of the CPU clock signal (314) due to the presence of static phase offset introduced by the PLL circuit (312).