| 摘要 |
<P>PROBLEM TO BE SOLVED: To obtain a clock feeding system which enables the non-interruption of data and phase matching in switching clock sources while the reliability of multiplexing is achieved. <P>SOLUTION: A scale of clock processing circuit for non-interruption switching is reduced by mounting distributed clock sources to each interface processing unit, mutually transmitting and reducing a frame pulse obtained by dividing the output of the clock source and a clock between interface processing units, matching phases for the frame pulse which are selected for transmitting the frame pulse to the other processing unit, and controlling clock jitter by a PLL circuit located in the interface processing unit. Moreover, a high precision clock source is preferentially selected by mounting a high precision clock source conforming to the SDH standard to the SDH system interface processing unit mounting a low precision clock source not conforming to this standard to the Ethernet (R) system interface processing unit. If high precision clock sources become defective completely, the lower precision clock sources are selected. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
