| 摘要 |
PURPOSE: To recover an accurate clock signal in a short time by correcting a phase error detected by a phase error detection section synchronously with a phase shift when a window phase control means shifts a phase of a time window. CONSTITUTION: When a DFT time window generating circuit 53 receives a window synchronizing signal from an output of a parallel/serial conversion circuit, the circuit 53 provides a window phase control signal WCONT corresponding to a state of a window phase in the DFT circuit to an output terminal based on the window synchronizing signal and also provides an output of a phase correction control signal PCONT corresponding to the window phase control signal WCONT to a phase error correction circuit 52A of a clock recovery circuit 52. In this case, the phase error correction circuit 52A corrects a phase of the phase control signal selected by a selection circuit 42A based on the phase correction control signal PCONT and provides an output of the result to a phase error detection circuit 42B. Thus, the phase error detection circuit 42B detects only a phase error unable to be eliminated by the window phase and it is given to a low pass filter 42C as phase error difference information. |
