ECC GENERATION CONTROLLING CIRCUIT FOR SELECTIVELY CONTROLLING ECC GENERATION FOR MICRO-PROCESSOR

摘要

PURPOSE: An ECC(Error Correction Code) generation controlling circuit for selectively controlling ECC generation for an address area is provided to selectively control the ECC generation for the specified address area by storing information for the address area to disable the ECC generation in a configuration register and using the information. CONSTITUTION: The first ECC generator(12) generates an ECC bit from the DMA(Direct Memory Access) write data. The first multiplexer(10) selectively outputs a CPU ECC bit or the ECC bit from the first ECC generator to a memory by responding to the first control signal. An address detector(14) generates an ECC disable signal and the second control signal for enabling the read ECC generation. The second ECC generator(20) generates the ECC bit from the ECC bit from the memory. The second multiplexer(18) selects/outputs the ECC bit from the second ECC generator or the memory to the CPU by responding to the second control signal. A memory controlling circuit(16) controls the ECC generation on a DMA write cycle for the corresponding address area by responding to the ECC disable signal.