发明名称 EFFICIENT MODULAR ADDER PERFORMING MODULAR ADDING OPERATION REGARDNESS OF RANGE OF INPUT VALUE, AND OPERATING METHOD THEREOF
摘要 PURPOSE: An efficient modular adder and an operating method thereof are provided to perform a modular adding operation fast by suggesting a modular adder circuit applicable to a DSP(Digital Signal Processor) or inserted into other system as an independent block. CONSTITUTION: If input values are inputted, the first adder block adds the inputted values. A control block makes the first multiplexer block output the output from the first adder block or a register block as sum. A calculator k block finds out the k by using an equation. A cal.m(k) block finds out the m(k) by using the equation. A cal.m(k-1) block finds out the m(k-1) by using the equation. The second adder block adds the output of the first multiplexer block and the cal.m(k) block. The third add block adds the output of the first multiplexer block and the cal.m(K-1) block. The fourth adder block adds the output of the second/third adder block. The second multiplexer block outputs/sends the output of the second/third adder block as the (x+y)mod(m) to the register block. A select-result block informs the modular operation completion of a signal processing system.
申请公布号 KR20040080523(A) 申请公布日期 2004.09.20
申请号 KR20030015343 申请日期 2003.03.12
申请人 KOREA ELECTRONICS TECHNOLOGY INSTITUTE 发明人 CHO, GYEONG YEON;CHOI, JONG CHAN;LEE, SEUNG EUN;OH, WON SEOK
分类号 G06F7/50;(IPC1-7):G06F7/50 主分类号 G06F7/50
代理机构 代理人
主权项
地址