Integrated circuit with gate-array interconnections routed over memory area

摘要

In an integrated circuit combining a gate array with memory on a single semiconductor substrate, the interconnecting lines are routed in multiple metalization layers. In each layer having both memory and gate-array interconnecting lines, the memory interconnecting lines are routed over the memory area, and the gate-array interconnecting lines are routed in a different direction over the gate-array area. In layers having only gate-array interconnecting lines, some of these lines pass over the memory area, being routed directly above power-supply lines or shield lines provided in the layer just below.