发明名称 Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states
摘要 A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for incrementing and decrementing a transition upcounter-downcounter controlling the oscillator. The system tolerates variation of the frequency of the incoming signal about a mean value, which has no effect on a clock signal to be extracted by means of a phase comparator or on the synthesized clock signal supplied by the oscillator if the incoming signal contains a high level of jitter and is supplied by a programmable frequency divider.
申请公布号 US6701445(B1) 申请公布日期 2004.03.02
申请号 US20000559524 申请日期 2000.04.28
申请人 FRANCE TELECOM 发明人 MAJOS JACQUES
分类号 H03L7/06;H03L7/087;H03L7/089;H03L7/091;H04L7/033;(IPC1-7):G06F1/08 主分类号 H03L7/06
代理机构 代理人
主权项
地址
您可能感兴趣的专利