| 摘要 |
PROBLEM TO BE SOLVED: To provide a DMA circuit with improved controllability as a whole system. SOLUTION: This DMA circuit has a read address register 105 for setting a read address; a write address register 106 for setting a write address; a logic sum register 203 for setting data; a logic operation selection register 303 for setting whether the read data are written as they are or subjected to logic sum operation; and a data processing circuit 301 for controlling processing to write the read data from the read address in the write address as they are, according to the set of the logic operation selection register 303, or to write the data obtained by the logic sum operation of the read data and the data set in the logic sum register 302 to the write address. COPYRIGHT: (C)2004,JPO
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